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HD74HC4538
Dual Precision Retriggerable/Resettable Monostable Multivibrators
REJ03D0654-0200 (Previous ADE-205-543) Rev.2.00 Mar 30, 2006
Description
Each multivibrator features both a negative, A, and a positive, B, transition triggered input, either of which can be used as an inhibit input. Also included is a clear input that when taken low resets the one short. The HD74HC4538 is retriggerable. That is, it may be triggered repeatedly while their outputs are generating a pulse and the pulse will be extended. Pulse width stability over a wide range of temperature. The output pulse equation is simply: tw = 0.7 (R) (C).
Features
* * * * * * High Speed Operation: tpd (A or B to Y) = 22 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 A max Low Quiescent Supply Current Ordering Information
Part Name HD74HC4538P HD74HC4538FPEL HD74HC4538RPEL Package Type DILP-16 pin SOP-16 pin (JEITA) SOP-16 pin (JEDEC) Package Code (Previous Code) PRDP0016AE-B (DP-16FV) PRSP0016DH-B (FP-16DAV) Package Abbreviation P FP -- EL (2,000 pcs/reel) EL (2,500 pcs/reel) Taping Abbreviation (Quantity)
PRSP0016DG-A RP (FP-16DNV) Note: Please consult the sales office for the above package availability.
Function Table
CD L H H H H Irrelevant Inputs A X L H L Outputs B X H Not triggered Not triggered Q L Q H
X:
Rev.2.00 Mar 30, 2006 page 1 of 13
HD74HC4538
Pin Arrangement
T1A T2A CDA AA BA QA QA GND 1 2 3 4 5 6 7 8 (Top view)
T1 T2 T1
16 VCC 15 T1B 14 T2B 13 CDB 12 AB 11 BB 10 QB 9 QB
CD
T2
A
CD
B
A
Q
B
Q
Q
Q
Logic Diagram
CX RX VCC T1A T2A
QA AA BA QA CDA CX RX VCC T1B T2B
QB AB BB QB CDB RX and CX are external components
Rev.2.00 Mar 30, 2006 page 2 of 13
HD74HC4538
Absolute Maximum Ratings
Item Supply voltage range Input voltage Output voltage DC input diode current DC input diode current pin 2, 14 DC output diode current DC current drain per pin DC current drain per VCC, GND Power dissipation per package Storage temperature Symbol VCC Vin Vout IIK IIK IOK Iout ICC, IGND PT Tstg Rating -0.5 to +7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 20 30 20 25 50 500 -65 to +150 Unit V V V mA mA mA mA mA mW C
Recommended Operating Conditions
Item Supply voltage Input / Output voltage Operating temperature Input rise / fall time Note:
*1
Symbol VCC VIN, VOUT Ta tr, tf
Ratings 2 to 6 0 to VCC -40 to 85 0 to 1000 0 to 500
Unit V V C ns
Conditions
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
0 to 400 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics.
Electrical Characteristics
Item Input voltage Symbol VCC (V) VIH 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 Min 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.18 5.68 -- -- -- -- -- -- -- Ta = 25C Typ Max -- -- -- -- -- -- 2.0 4.5 6.0 -- -- 0.0 0.0 0.0 -- -- -- -- -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.26 0.26 0.1 130 Ta = -40 to+85C Unit Min Max 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.13 5.63 -- -- -- -- -- -- -- -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.33 0.33 1.0 220 V Test Conditions
VIL
V
Output voltage
VOH
V
Vin = VIH or VIL IOH = -20 A
VOL
V
IOH = -4 mA IOH = -5.2 mA Vin = VIH or VIL IOL = 20 A
IOL = 4 mA IOL = 5.2 mA A Vin = VCC or GND A Vin = VCC or GND, QA = QB = GND, Iout = 0 A A Vin = VCC or GND, QA = QB = VCC Pin 2, 14 = 0.5 VCC
Input current Quiescent supply current (standby state) Current drain (active state)
Iin ICC
ICC
6.0
--
--
130
--
220
Rev.2.00 Mar 30, 2006 page 3 of 13
HD74HC4538
Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Item Propagation delay time Symbol VCC (V) tPLH 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 3.0 5.0 3.0 5.0 3.0 5.0 3.0 5.0 5.0 Ta = 25C Min Typ Max -- -- -- -- -- -- -- -- -- -- -- -- 80 16 14 -- -- -- -- -- -- -- -- -- -- 22 -- -- 23 -- -- 17 -- -- -- -- -- -- -- 150 100 -- 1.3 -- 9 -- 70 0.1 235 47 40 260 52 44 235 47 40 235 47 40 -- -- -- -- -- -- -- -- -- -- -- -- Ta = -40 to +85C Min Max -- -- -- -- -- -- -- -- -- -- -- -- 100 20 17 -- -- -- -- -- -- -- -- -- 295 59 50 325 65 55 295 59 50 295 59 50 -- -- -- -- -- -- -- -- -- -- -- -- Unit ns Test Conditions A or B to Q
tPHL
ns
A or B to Q
tPHL
ns
CD to Q
tPLH
ns
CD to Q
Pulse width
tw
ns
A, B, CD
Output pulse width
tWQ
ns s s s %
RX = 1 k, CX = 12 pF RX = 10 k, CX = 100 pF RX = 10 k, CX = 1000 pF RX = 10 k, CX = 10000 pF RX = 10 k, CX = 1000 pF
Pulse width match between circuits in the same package
tWQ
Caution in use: In order to prevent any malfunctions due to noise, connect a high frequency performance capacitor between VCC and GND, and keep the wiring between the External components and Cext, Rext/Cext pins as short as possible.
Test Circuit
VCC Input A Pulse Generator Zout = 50 Input B Pulse Generator Zout = 50 Input Clear Pulse Generator Zout = 50 Cext Rext/Cext Q VCC Cext Rext Output
See Function Table
CL = 50 pF Output Q Clear
CL = 50 pF
Note : 1. CL includes probe and jig capacitance.
Rev.2.00 Mar 30, 2006 page 4 of 13
HD74HC4538
Circuit Operation
Figure 3 shows the HC4538 configured in the retriggerable mode. Briefly, the device operates as follows (refer to figure 1): In the quiescent state, the external timing capacitor, CX, is charged to VCC. When a trigger occurs, the Q output goes high and CX discharges quickly to the lower references voltage (Vref Lower 1/3 VCC). CX then charges, through RX, back up to the upper reference voltage (Vref Upper 2/3 VCC), at which point the one-shot has timed out and the Q output goes low. The following, more detailed description of the circuit operation refers to both the function diagram (figure 1) and the timing diagram (figure 2) Quiescent State In the quiescent state, before an input trigger appears; the output latch is high and the reset latch is high (1 in figure 2). Thus the Q output (pin 6 or 10) of the monostable multivibrator is low (2 figure 2). The output of the trigger-control circuit is low (3), and transistors M1, M2, and M3 are turned off. The external timing capacitor, CX, is charged to VCC (4), and the upper reference circuit has a low output (5). Transistor M4 is turned on and analog switch S1 is turned off. Thus the lower reference circuit has VCC at the noninverting input and a resulting low output (6). In addition, the output of the trigger-control reset circuit is low. Trigger Operation The HC4538 is triggered by either a rising-edge signal as input A (7) or a falling-edge signal at input B (8), with the unused trigger input and the Reset input held at the voltage levels shown in the Function Table. Either trigger signal will cause the output of the trigger-control circuit to go high (9). The trigger-control circuit going high simultaneously initiates three events. First, the output latch goes low, thus taking the Q output of the HC4538 to a high state (10). Second, transistor M3 is turned on, which allows the external timing capacitor, CX, to rapidly discharge toward ground (11). (Note that the voltage across CX appears at the input of the upper reference circuit comparator). Third, transistor M4 is turned off and analog switch S1 is turned on, thus allowing the voltage across CX to also appear at the input of the lower reference circuit comparator. When CX discharges to the reference voltage of the lower reference circuit (12), the outputs of both reference circuits will be high (13). The trigger-control circuit flip-flop to a low state (14). This turns transistor M3 off again, allowing CX to begin to charge back up toward VCC, with a time constant t = RXCX (15). In addition, transistor M4 is turned on and analog switch S1 is turned off. Thus a high voltage level is applied to the input of the lower reference circuit comparator, causing its output to go low (16). The monostable multivibrator may be retriggered at any time after the trigger-control circuit goes low. When CX charges up to the reference voltage of the upper reference circuit (17), the output of the upper reference circuit goes low (18). This causes the output latch to toggle, taking the Q output of the HC4538 to a low state (19), and completing the time-out cycle. Reset Operation A low voltage applied to the Reset pin always forces the Q output of the HC4538 to a low state. The timing diagram illustrates the case in which reset occurs (20) while CX is charging up toward the reference voltage of the upper reference circuit (21). When a reset occurs, the output of the reset latch goes low (22), turning on transistor M1. Thus CX is allowed to quickly charge up to VCC (23) to await the next trigger signal. Retrigger Operation When used in the retriggerable mode (figure 3), the HC4538 may be retriggered during timing out of the output pulse at any time after the trigger-control circuit flip-flop has been reset (24). Because the trigger-control circuit flip-flop resets shortly after CX has discharged to the reference voltage of the lower reference circuit (25), the minimum retrigger time, trr (Switching Waveform 1) is a function of internal propagation delays and the discharge time of CX: Figure 4 shows the device configured in the non-retriggerable mode.
Rev.2.00 Mar 30, 2006 page 5 of 13
HD74HC4538 Power-Down Considerations Large values of CX may cause problems when powering down the HC4538 because of the amount of energy stored in the capacitor. When a system containing this device is powered down, the capacitor may discharge from VCC through the input protection diodes at pin 2 or pin 14. Current through the protection diodes must be limited to 30 mA; therefore, the turn-off time of the VCC power supply must not be faster than t = VCC*CX/(30 mA). For example, if VCC = 5 V and CX = 15 F, the VCC supply must turn off no faster than t = (5 V)*(15 F)/30 mA = 2.5 ms. This is usually not a problem because power supplies are heavily filtered and cannot discharge at this rate. When a more rapid decrease of VCC to zero voltage occurs, the HC4538 may sustain damage. To avoid this possibility, use an external clamping diode.
VCC RX T2 CX 2, 14
VCC M2
M1 2k
Upper Reference Circuit
Output Latch
M3
+ -
Vref Upper S1 VCC M4 Lower Reference Circuit 7, 9 6, 10 Q
+ -
4, 12 A B 5, 11 CQ CR Trigger-Control Reset Circuit Trigger-Control Circuit Vref Lower
Q
3, 13 CD
Reset Latch
Figure 1. Function Diagram
Rev.2.00 Mar 30, 2006 page 6 of 13
HD74HC4538
Quiescent State
Trigger Cycle (A Input)
Trigger Cycle (B Input)
Reset trr
Retrigger
7
Trigger Input A (Pin 4 or 12) Trigger Input B (Pin 5 or 11)
8
Reset Input CD (Pin 3 or 13)
21
9
24 14 11 15 20 23
Trigger-Control Circuit Output T2 Input (Pin 2 or 14) Upper Reference Circuit Output Lower Reference Circuit Output Reset Latch Output
3 4 12
17
Vref Lower 13
5 13 6 16
Vref Upper
25
1 22 10
Q Output (Pin 6 or 10)
2
19
tWQ tW (H) A 50%
tWQ
tWQ+trr
tW (L) B tPLH Q 50% tPHL Q 50% tPHL tWQ 50% tPLH
A trr B tf CD tTLH Q tTHL Q 90% 10% 90% 10% tPLH 50% 50% tW (L) tPHL 50% tr 90% 10% tWQ+trr 50% (Retriggered Pulse) 50%
Figure 2. Timing Diagram
Rev.2.00 Mar 30, 2006 page 7 of 13
HD74HC4538
CX RX VCC T1 T2
A Rising-Edge Trigger B
Q
Q
CD
CX
RX VCC
T1
T2
A B Falling-Edge Trigger CD
Q
Q
Figure 3. Retriggerable Monostable Circuitry
Rev.2.00 Mar 30, 2006 page 8 of 13
HD74HC4538
CX RX VCC T1 T2
A Rising-Edge Trigger B
Q
Q
CD
CX
RX VCC
T1
T2
A B Falling-Edge Trigger CD
Q
Q
Figure 4. Nonritriggerable Monostable Circuitry
Application Data
10000.0
Vcc = 2.5 V
Output Pulse Width twQ (s)
1000.0
100.0
10.0
Rext
1.0 1 k 10 k 100 k 1 M
0.1 102 103 104 105 106 107
Timing Capacitance Cext (pF)
Rev.2.00 Mar 30, 2006 page 9 of 13
HD74HC4538
Vcc = 3.3 V
10000.0
twQ (s) Output Pulse Width
1000.0
100.0
10.0
Rext
1.0 1 k 10 k 100 k 1 M
0.1 102 103 104 105 106 107
Timing Capacitance Cext (pF)
Vcc = 5.0 V
10000.0
Output Pulse Width twQ (s)
1000.0
100.0
10.0
Rext
1.0 1 k 10 k 100 k 1 M
0.1 102 103 104 105 106 107
Timing Capacitance Cext (pF)
Rev.2.00 Mar 30, 2006 page 10 of 13
HD74HC4538
Rext = 2 k
1.2
Coefficient of Output Pulse Width K
Cext 1.1
1000 pF 10000 pF 100000 pF 1000000 pF
1.0
0.9
0.8
0.7 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Supply Voltage Vcc (V)
1.2
Rext = 10 k Cext
Coefficient of Output Pulse Width K
1.1
1000 pF 10000 pF 100000 pF 1000000 pF
1.0
0.9
0.8
0.7
0.6 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Supply Voltage Vcc (V)
Rev.2.00 Mar 30, 2006 page 11 of 13
HD74HC4538
Package Dimensions
JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g
D
16
9
1 0.89 b3
8
Z
A1
A
E
Reference Symbol
Dimension in Millimeters
Min
e
bp
e1
c
( Ni/Pd/Au plating )
e1 D E A A1 bp b3 c e Z L
Nom Max 7.62 19.2 20.32 6.3 7.4 5.06
L
0.51 0.40 0.48 0.56 1.30 0.19 0.25 0.31 0 15 2.29 2.54 2.79 1.12 2.54
JEITA Package Code P-SOP16-5.5x10.06-1.27
RENESAS Code PRSP0016DH-B
Previous Code FP-16DAV
MASS[Typ.] 0.24g
*1
D F 9
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
*2
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
8 bp x M L1
Reference Dimension in Millimeters Symbol
c
A1
y
L
Detail F
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
Min Nom Max 10.06 10.5 5.50
0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 0.20 0.25 0 8 7.50 7.80 8.00 1.27 0.12 0.15 0.80 0.50 0.70 0.90 1.15
Rev.2.00 Mar 30, 2006 page 12 of 13
A
HD74HC4538
JEITA Package Code P-SOP16-3.95x9.9-1.27 RENESAS Code PRSP0016DG-A Previous Code FP-16DNV MASS[Typ.] 0.15g
*1
D 9
F
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
E HE
Index mark
*2
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
c
8 bp x M L1
Reference Dimension in Millimeters Symbol
A1
L
y
Detail F
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
Min Nom Max 9.90 10.30 3.95
0.10 0.14 0.25 1.75 0.34 0.40 0.46 0.15 0.20 0.25 0 8 5.80 6.10 6.20 1.27 0.25 0.15 0.635 0.40 0.60 1.27 1.08
Rev.2.00 Mar 30, 2006 page 13 of 13
A
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